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Features
* Incorporates the ARM7TDMI(R) ARM(R) Thumb(R) Processor
- 72 MIPS at 80MHz - EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories - One 256 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed - 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Matrix Speed (Configured in blocks of 96 KB and 64 KB with separate AHB slaves) External Bus Interface (EBI) - Supports SDRAM, Static Memory, NAND Flash/SmartMedia(R) and CompactFlash(R) USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM Metal Programmable Block - 450000 Gates Metal Programmable Logic for CAP7 - Two 4Kbytes Dual Port RAMs for buffer space - High Connectivity for up to 4 AHB Masters and 4 dedicated/16 muxed Slaves for CAP7 - Up to twenty-eight AIC interrupt inputs - Access to Atmel AHB/APB library - Up to 90 dedicated I/Os - Optional PIO controller for up to 32 of the available I/Os 10-bit Analog to Digital Converter (ADC) - Up to 8 multiplexed channels - 440 kSample / s Bus Matrix - Six-layer, 32-bit Matrix, Allowing 15.4 Gbps of On-chip Bus Bandwidth Fully-featured System Controller, including - Reset Controller, Shut Down Controller - Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes - Clock Generator - Advanced Power Management Controller (APMC) - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer and Real-Time Timer Boot Mode Select Option and Remap Command Reset Controller - Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shut Down Controller - Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) - 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - Internal 32kHz RC oscillator for fast start-up - 8 to 16 MHz On-chip Oscillator, 50 to 100 MHz PLL, and 80 to 240 MHz PLL Advanced Power Management Controller (APMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Four Programmable External Clock Output Signals
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Customizable Microcontroller
AT91CAP7S450A
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Preliminary Summary
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* Advanced Interrupt Controller (AIC)
- Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Two External Interrupt Sources and one Fast Interrupt Source, Spurious interrupt protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit interval Timer plus 12-bit interval Counter Watchdog Timer (WDT) - Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-Time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler One 32-bit Parallel Input/Output Controllers (PIOA) - 32 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os each - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor, Bus Holder and Synchronous Output - Additional PIO Controllers can be added in the Metal Programmable Block 22 Peripheral DMA Controller Channels (PDC) Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation, Manchester Encoding/Decoding Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, External Peripheral Chip Select - Synchronous Communications at up to 80Mbits/sec One Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability IEEE 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: 1.08V to 1.32V for VDDCORE and VDDBU 1.08V to 1.32V for VDDOSC, VDDOSC32, and VDDPLLB 3.0V to 3.6V for VDDPLLA and VDDIO 3.0V to 3.6V for AVDD (ADC) Package Options: 144 LQFP, 176 LQFP, 208 PQFP, 144 LFBGA, 176TFBGA, 208 TFBGA, 225 LFBGA
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1. Description
The AT91CAP7 semi-custom System on a Chip (SoC) provides Atmel's ASIC customers a microcontroller platform for rapid integration of their own Intellectual Property (IP) in metal programmable cells. Fabrication time is greatly reduced since only the metal layers will remain to be generated on the silicon. In addition to 450K gates of metal programmable logic, the AT91CAP7 includes an ARM7TDMI core with a high-speed bus (AHB), on-chip ROM and SRAM, a full-featured system controller, and various general-purpose peripheral subsystems. It is implemented in a 130 nm CMOS 1.2V process and supports 3.3V I/O.
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AT91CAP7S450A [Preliminary]
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AT91CAP7S450A [Preliminary]
2. Block Diagram
Figure 2-1.
JTAGSEL TDI TDO TMS TCK NTRST
AT91CAP7 Block Diagram
JTAG Boundary Scan
ICE
ARM7TDMI Processor AHB Wrapper
BMS D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A22 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NANDOE NANDWE NCS6 NCS7 D16-D31
System Controller TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA AIC
PIO
DBGU PDC
Fast SRAM 96K bytes
EBI CompactFlash NAND Flash
PLLA PLLB PMC
Fast SRAM 64K bytes
XIN XOUT
OSC
Fast ROM 256K bytes PIT Peripheral Bridge
6-layer AHB Matrix
SDRAM Controller Static Memory Controller
WDT RC OSC XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST PIOA POR RSTC POR OSC
GPBREG RTT SHDWC
Peripheral DMA Controller
4 4 Slaves
Masters APB
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 NPCS00 NPCS01 NPCS02 NPCS03 MISO0 MOSI0 SPCK0 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 ADTRG
USART0 PDC User Metal Programmable Block 450 KG
PIO
MPIO81-MPIO00
USART1 PDC Pin Availablility Depends on Package Selection
SPI
PIO PIO
PDC Timer Counter TC0 TC1 TC2
2x DPRAM 4K bytes
MPIO82 / AD0 MPIO83 / AD1 MPIO84 / AD2 MPIO85 / AD3 MPIO86 / AD4 MPIO87 / AD5 MPIO88 / AD6 MPIO89 / AD7 PDC
10-Bit ADC
Transceiver
FIFO ADVREF USB Device PDC
DDM DDP
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3. Signal Description
Table 3-1.
Signal Name
Signal Description by Peripheral
Function Power Supplies Type Active Level Comments
VDDCORE VDDBU VDDIO VDDPLLA VDDPLLB VDDOSC VDDOSC32 AVDD GND GNDPLLA GNDPLLB GNDOSC GNDOSC32 GNDBU AGND
Core Chip Power Supply Backup Power Supply, includes Backup I/O and Logic I/O Lines Power Supply, except Backup I/O PLL A Power Supply PLL B Power Supply Oscillator Power Supply Oscillator Power Supply ADC Analog Power Supply VDDIO and VDDCORE Ground PLL Ground A PLL Ground B Main Oscillator Ground 32 kHz Oscillator Ground Backup Ground ADC Analog Ground
Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground
1.08V to 1.32V 1.08V to 1.32V, required for all operational modes. 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 1.08V to 1.32V, required for all operational modes. 3.0V to 3.6V
Clocks, Oscillators and PLLs XIN Main Oscillator Input Input Analog Connect to an external crystal or drive with a 1.2V nominal square wave clock input Connect to external crystal or leave unconnected Connect to a 32768Hz crystal or drive with a 1.2V, 32kHz nominal square wave Input, leave unconnected (32kHz RC OSC only) Connect to a 32768Hz crystal or leave unconnected Must connect to an appropriate RC network for proper PLL operation access via PIOA
XOUT
Main Oscillator Output
Output
Analog
XIN32
Slow Clock Oscillator Input
Input
Analog
XOUT32
Slow Clock Oscillator Output
Output
Analog
PLLRCA PCK0 - PCK3
PLL A Filter Programmable Clock Output
Input Output
Analog Clock
Analog to Digital Converter AD0 ADC Input 0 An. Input Analog shared with MPIO82
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AT91CAP7S450A [Preliminary]
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AT91CAP7S450A [Preliminary]
Table 3-1.
Signal Name AD1 AD2 AD3 AD4 AD5 AD6 AD7
Signal Description by Peripheral (Continued)
Function ADC Input 1 ADC Input 2 ADC Input 3 ADC Input 4 ADC Input 5 ADC Input 6 ADC Input 7 Type An. Input An. Input An. Input An. Input An. Input An. Input An. Input Active Level Analog Analog Analog Analog Analog Analog Analog Comments shared with MPIO83 shared with MPIO84 shared with MPIO85 shared with MPIO86 shared with MPIO87 shared with MPIO88 shared with MPIO89 Do not leave floating - Connect to AVDD externally or another analog voltage reference up to 3.3V Tie to AGND externally if enabled and not used - access via PIOA
ADVREF
ADC Voltage Reference Input
An. Input
Analog
ADTRG
ADC External Trigger
Dig. Input
High
Shutdown, Wake-up Logic SHDW WKUP0WKUP0 Shut-Down Control Wake-Up Input ICE and JTAG TCK TDI TDO TMS NTRST JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection Reset/Test NRST Microcontroller Reset I/O Low Pull-up resistor Accept between 0V and VDDBU Pull-down resistor Accept between 0V and VDDBU Pull-up resistor 1=embedded ROM 0=EBI CS0 Input Input Output Input Input Input Low High Pull-down resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-down resistor Output Input High Driven at 0V only. Do not tie over VDDBU Accept between 0V and VDDBU.
TST
Chip Test Enable
Input
High
BMS
Boot Mode Select Debug Unit - DBGU
Input
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
access via PIOA access via PIOA
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Table 3-1.
Signal Name
Signal Description by Peripheral (Continued)
Function Type Advanced Interrupt Controller - AIC Active Level Comments
IRQ0 - IRQ1 FIQ
External Interrupt Inputs Fast Interrupt Input PIO Controller - PIOA
Input Input
High High
access via PIOA access via PIOA
Pulled-up input at reset PA0 - PA31 Parallel IO Controller A I/O
External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset; access D16 - D31 via PIOA 0 at reset; access A23-A25 via PIOA access via PIOA
Static Memory Controller - SMC NCS0 - NCS7 NWR0 -NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Support NANDCS NANDOE NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select Output Output Output Output High Low Output Output Output Low Low Low access via PIOA access via PIOA Output Output Output Output Output Output Output Low Low Low Low Low Low access via PIOA access via PIOA access via PIOA Low Low Low Low Low access NCS4 - NCS7 via PIOA
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AT91CAP7S450A [Preliminary]
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AT91CAP7S450A [Preliminary]
Table 3-1.
Signal Name SDWE RAS - CAS SDA10
Signal Description by Peripheral (Continued)
Function SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Type Output Output Output Active Level Low Low Comments
Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O access via PIOA access via PIOA access via PIOA I/O I/O Input Output Input access via PIOA access via PIOA access via PIOA access via PIOA access via PIOA
Serial Peripheral Interface - SPI SPI_MISO SPI_MOSI SPI_SPCK SPI_NPCS0 SPI_NPCS1 - SPI_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select USB Device Port DDM DDP USB Device Port Data USB Device Port Data + Analog Analog I/O I/O I/O I/O Output Low Low access via PIOA access via PIOA access via PIOA access via PIOA access via PIOA
Metal Programmable Block - MPB MPIO0 - MPIO89 MPB general purpose I/O I/O
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4. Package and Pinout
The AT91CAP7 is available in a variety of RoHS-compliant packages. The following AT91CAP7 package options have pre-defined, fixed pinouts listed in various sections below: * 225-ball LFBGA 13x13x1.4mm, 0.8 mm ball pitch * 208-PQFP 28x28x3.4mm, 0.5 mm pin pitch * 176-LQFP 20x20x1.4 mm, 0.5 mm pin pitch * 144-LQFP 20x20x1.4 mm, 0.5 mm pin pitch. The following packages are also available for AT91CAP7 on advance request. These package options may require custom BGA substrate design. The pinouts for these packages are not yet published but will be similar to their QFP counterparts listed above. * 208-TFBGA 15x15x1.2mm, 0.8 mm ball pitch * 176-TFBGA 10x10 12x12x1.2mm, 0.8 mm ball pitch * 144-LFBGA 10x10x1.4mm, 0.8 mm ball pitch
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AT91CAP7S450A [Preliminary]
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AT91CAP7S450A [Preliminary]
4.1 Package Selection Guide
The following table summarizes the functions and interfaces available in each package.
Table 4-1.
I/O Features
AT91CAP7 Package Selection Guide
225 LFBGA 82 8 32 16 or 32 26 yes yes (8 cs) yes yes yes yes yes yes yes yes (4 cs) yes 2 1 yes yes 4 208 PQFP 44 5 32 16 or 32 25 yes yes (8 cs) yes yes yes yes yes yes yes yes (4 cs) yes 2 1 yes yes 4 176 LQFP 33 8 13 16 23 yes yes (7 cs) yes (1 ce) yes yes yes yes yes no yes (3 cs) no 2 1 yes yes no 144 LQFP 16 4 11 16 23 no yes (5 cs) yes (1 cs/ce) yes yes yes yes yes no yes (1 cs) no 1 1 yes yes no
MPIO pins available MPIO / ADC Channels Total PIOA pins available EBI Data Bus Width EBI Address Bus Width SDRAM Static Memory Compact Flash NAND Flash Boot Mode Select ADC External Trigger Debug Unit USART0 USART1 SPI Timer I/O External IRQ's External FIQ Main Clock Oscillator 32 kHz Oscillator External APMC Clocks
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4.2
Mechanical Overview of the 225-ball LFBGA Package
Figure 4-1 shows the orientation of the 225-ball LFBGA Package. A detailed mechanical description is given in the Mechanical Characteristics section of the product datasheet. Figure 4-1. 225-ball LFBGA Pinout (Bottom View)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P R
4.3
225-ball LFBGA Package Pinout
Warning: This package pinout is preliminary and is subject to change. AT91CAP7 Pinout for 225-ball LFBGA Package
Signal Name MPIO81 PA9 PA8 MPIO45 MPIO25 PA4 MPIO13 MPIO23 MPIO20 MPIO43 MPIO41 MPIO40 MPIO03 MPIO76 A18 A6 MPIO49 MPIO48 MPIO46 PA5 MPIO24 MPIO15 Pin D13 D14 D15 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F1 F2 F3 F4 Signal Name MPIO01 MPIO75 MPIO34 A3 A4 MPIO80 MPIO56 BMS PA10 NCS2 MPIO09 MPIO08 MPIO05 MPIO39 MPIO00 MPIO35 MPIO32 SDA10 SDWE A2 MPIO55 SDRAMCKE Pin H10 H11 H12 H13 H14 H15 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 K1 Signal Name VDDC D5 PA3 PA2 A9 A10 D7 D6 MPIO31 D8 DDP D2 GND GND GND A12 MPIO17 PA0 PA1 MPIO19 A8 MPIO29 Pin M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Signal Name PA22 MPIO89/AD7 PA14 MPIO70 GNDPLLA TDO TDI PA28 NWR0 MPIO61 MPIO64 VDDBU XOUT32 MPIO85/AD3 AVDD PA20 PA13 MPIO67 NRD PLLRCA XIN VDDPLLA
Table 4-2.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7
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AT91CAP7S450A [Preliminary]
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AT91CAP7S450A [Preliminary]
Table 4-2.
Pin B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
AT91CAP7 Pinout for 225-ball LFBGA Package (Continued)
Signal Name MPIO11 MPIO22 MPIO44 MPIO06 MPIO04 MPIO37 MPIO74 A20 MPIO52 NCS3 MPIO50 MPIO79 PA7 MPIO27 PA6 MPIO12 MPIO21 MPIO07 MPIO38 MPIO78 A22 A21 A17 MPIO54 A5 A7 NCS0 MPIO51 MPIO47 NWR3 MPIO14 MPIO10 MPIO42 MPIO77 MPIO02 Pin F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H7 H8 H9 Signal Name MPIO53 A0 VDDIO MPIO26 VDDIO A19 MPIO36 MPIO33 A14 A16 A15 MPIO28 SDRAMCLK A1 D14 D15 VDDC GND GND GND VDDIO RAS N/C A11 CAS A13 D10 D9 D13 D11 D12 VDDIO GND GND GND Pin K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 Signal Name MPIO30 MPIO60 MPIO59 MPIO62 WKUP0 VDDIO VDDC VDDIO XOUT PA25 TMS PA24 MPIO16 MPIO18 MPIO57 MPIO58 D1 MPIO65 VDDOSC32 GNDBU MPIO86/AD4 NCS1 PA17 GNDPLLB PA31 NTRST MPIO73 PA30 PA18 DDM MPIO63 D0 XIN32 GNDOSC32 MPIO83/AD1 Pin N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Signal Name PA29 NRST D4 D3 SHDW TST MPIO82/AD0 MPIO87/AD5 PA21 PA16 PA11 MPIO68 GNDOSC NWR1 VDDOSC TCK PA27 JTAGSEL ADVREF MPIO84/AD2 MPIO88/AD6 AGND PA23 PA19 PA15 PA12 MPIO66 MPIO69 MPIO71 MPIO72 VDDPLLB PA26
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4.4
Mechanical Overview of the 208-pin PQFP Package
Figure 4-2 shows the orientation of the 208-pin PQFP Package. A detailed mechanical description is given in the Mechanical Characteristics section of the product datasheet. Figure 4-2. 208-pin PQFP Pinout (Top View)
208 1
157 156
52 53 104
105
4.5
208-pin PQFP Package Pinout
Warning: The package pinout is preliminary and is subject to change. AT91CAP7 Pinout for 208-pin PQFP Package
Signal Name NTRST TDI PA31 TDO PA30 TMS PA29 TCK PA28 GND PA27 VDDIO PA26 NRST PA25 NWR0 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal Name MPIO01 MPIO02 VDDIO GND MPIO03 MPIO04 MPIO05 MPIO41 MPIO06 MPIO42 MPIO07 MPIO43 GND GND MPIO44 VDDIO Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal Name A7 GND VDDIO A6 A5 VDDCORE MPIO55 A4 MPIO56 GND NCS2 A3 SDRAMCKE A2 SDWE VDDIO Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 Signal Name VDDOSC32 XIN32 XOUT32 GNDOSC32 VDDBU SHDW WKUP0 JTAGSEL TST GNDBU ADVREF MPIO82/AD0 MPIO83/AD1 MPIO84/AD2 MPIO85/AD3 MPIO86/AD4
Table 4-3.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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AT91CAP7S450A [Preliminary]
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AT91CAP7S450A [Preliminary]
Table 4-3.
Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
AT91CAP7 Pinout for 208-pin PQFP Package (Continued)
Signal Name PA24 PA0 MPIO16 PA1 MPIO17 VDDCORE MPIO18 GND MPIO19 PA2 PA3 A8 A9 VDDIO A10 A11 A12 A13 A14 VDDCORE GND GND CAS A15 RAS A16 SDA10 VDDIO A17 A18 A19 A20 A21 GND A22 MPIO00 Pin 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Signal Name MPIO20 MPIO08 MPIO21 MPIO09 MPIO22 MPIO10 MPIO23 VDDCORE VDDIO MPIO11 GND MPIO12 MPIO13 MPIO14 MPIO15 PA4 NWR3 PA5 MPIO24 GND MPIO25 PA6 MPIO26 PA7 MPIO27 VDDIO MPIO45 VDDCORE MPIO46 PA8 PA9 GND PA10 NCS3 NCS0 BMS Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Signal Name SDRAMCLK A1 MPIO28 GND A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 GND D6 VDDIO D5 MPIO29 GND MPIO30 MPIO31 MPIO57 VDDCORE MPIO58 GND MPIO59 DDM DDP MPIO60 VDDIO D4 D3 D2 D1 D0 Pin 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Name AVDD AGND GND PA23 VDDIO PA22 GND PA21 NCS1 PA20 VDDCORE PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 GND VDDCORE GND NWR1 NRD VDDIO VDDPLLB GNDPLLB GNDOSC XIN XOUT VDDOSC VDDPLLA GNDPLLA PLLRCA GNDPLLA
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4.6
Mechanical Overview of the 176-pin LQFP Package
Figure 4-3 shows the orientation of the 176-pin LQFP Package. A detailed mechanical description is given in the Mechanical Characteristics section of the product datasheet. Figure 4-3. 176-pin LQFP Pinout (Top View)
176
133
1
132
44
89
45
88
4.7
176-pin LQFP Package Pinout
Warning: The package pinout is preliminary and is subject to change. AT91CAP7 Pinout for 176-pin LQFP Package
Signal Name NTRST TDI TDO TMS TCK GND VDDIO NRST NWR0 PA0 MPIO16 PA1 MPIO17 VDDCORE MPIO18 GND MPIO19 PA2 Pin 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Signal Name MPIO01 MPIO02 VDDIO GND MPIO03 MPIO04 MPIO05 MPIO06 MPIO07 GND VDDIO MPIO20 MPIO8 MPIO21 MPIO09 MPIO22 MPIO10 MPIO23 Pin 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Signal Name A7 GND VDDIO A6 A5 VDDCORE A4 GND A3 SDRAMCKE A2 SDWE VDDIO SDRAMCLK A1 MPIO28 GND A0 Pin 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Signal Name VDDOSC32 XIN32 XOUT32 GNDOSC32 VDDBU SHDW WKUP0 JTAGSEL TST GNDBU ADVREF MPIO82/AD0 MPIO83/AD1 MPIO84/AD2 MPIO85/AD3 MPIO86/AD4 MPIO87/AD5 MPIO88/AD6
Table 4-4.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
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AT91CAP7S450A [Preliminary]
5119DS-CAP-05/09
AT91CAP7S450A [Preliminary]
Table 4-4.
Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
AT91CAP7 Pinout for 176-pin LQFP Package (Continued)
Signal Name PA3 A8 A9 VDDIO A10 A11 A12 A13 A14 VDDCORE GND CAS A15 RAS A16 SDA10 VDDIO MPIO32 A17 A18 A19 A20 A21 GND A22 MPIO00 Pin 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Signal Name VDDCORE MPIO11 GND MPIO12 MPIO13 MPIO14 MPIO15 PA4 NWR3 PA5 MPIO24 GND MPIO25 PA6 MPIO26 PA7 MPIO27 VDDIO VDDCORE PA8 PA9 GND PA10 NCS3 NCS0 BMS Pin 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal Name D15 D14 D13 D12 D11 D10 D9 D8 D7 GND D6 D5 MPIO29 GND MPIO30 MPIO31 VDDCORE GND DDM DDP VDDIO D4 D3 D2 D1 D0 Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Signal Name MPIO89/AD7 AVDD AGND GND VDDIO GND NCS1 VDDCORE PA12 PA11 GND VDDCORE GND NWR1 NRD VDDIO VDDPLLB GNDPLLB GNDOSC XIN XOUT VDDOSC VDDPLLA GNDPLLA PLLRCA GNDPLLA
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4.8
Mechanical Overview of the 144-pin LQFP Package
Figure 4-4 shows the orientation of the 144-pin LQFP Package. A detailed mechanical description is given in the Mechanical Characteristics section of the product datasheet. Figure 4-4. 144-pin LQFP Pinout (Top View)
144
108
1
107
36
73
37
72
4.9
144-pin LQFP Package Pinout
Warning: This package pinout is preliminary and is subject to change. AT91CAP7 Pinout for 144-pin LQFP Package
Signal Name NTRST TDI TDO TMS TCK GND VDDIO NRST NWR0 PA0 PA1 VDDCORE GND PA2 PA3 A8 A9 VDDIO A10 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Signal Name MPIO01 MPIO02 VDDIO GND MPIO03 MPIO04 MPIO05 MPIO06 MPIO07 GND VDDIO MPIO8 MPIO09 MPIO10 VDDCORE MPIO11 GND MPIO12 MPIO13 Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Signal Name A7 GND VDDIO A6 A5 VDDCORE A4 GND A3 A2 VDDIO A1 GND A0 D15 D14 D13 D12 D11 Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Signal Name VDDOSC32 XIN32 XOUT32 GNDOSC32 VDDBU SHDW WKUP0 JTAGSEL TST GNDBU ADVREF MPIO82/AD0 MPIO83/AD1 MPIO84/AD2 MPIO85/AD3 AVDD AGND GND VDDIO
Table 4-5.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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Table 4-5.
Pin 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A11 A12 A13 A14 VDDCORE GND A15 A16 VDDIO A17 A18 A19 A20 A21 GND A22 MPIO00
AT91CAP7 Pinout for 144-pin LQFP Package (Continued)
Signal Name Pin 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal Name MPIO14 MPIO15 PA4 NWR3 PA5 GND PA6 PA7 VDDIO VDDCORE PA8 PA9 GND PA10 NCS3 NCS0 BMS Pin 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Signal Name D10 D9 D8 D7 D6 D5 GND VDDCORE GND DDM DDP VDDIO D4 D3 D2 D1 D0 Pin 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Signal Name GND VDDCORE GND VDDCORE NWR1 NRD VDDIO VDDPLLB GNDPLLB GNDOSC XIN XOUT VDDOSC VDDPLLA GNDPLLA PLLRCA GNDPLLA
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5. Power Considerations
5.1 Power Supplies
The AT91CAP7 has several types of power supply pins: * VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V (1.2V nominal). The associated ground pins for this supply and the VDDIO supply are the GND pins. * VDDIO pins: Power the non-backup I/O lines; voltage ranges between 3.0V and 3.6V (3.3V nominal). The associated ground pins for this supply and the VDDCORE supply are the GND pins. * VDDBU pin: Powers the RC oscillator, Backup I/O and part of the System Controller; voltage ranges from 1.08V and 1.32V, (1.2V nominal). The associated ground pin for this supply is the GNDBU pin. Required for all operational modes. * VDDPLLA pin: Powers the PLLA cell; voltage ranges from 3.0V and 3.6V (3.3V nominal). The associated ground pin for this supply is the GNDPLLA pin. * VDDPLLB pin: Powers the PLLB cell and related internal loop filter cell; voltage ranges from 1.08V and 1.32V (1.2V nominal). The associated ground pin for this supply is the GNDPLLB pin. * VDDOSC pins: Powers the Main Oscillator cell; voltage ranges from 1.08V and 1.32V (1.2V nominal). The associated ground pin for this supply is the GNDOSC pin. * VDDOSC32 pins: Powers the 32 kHz oscillator cell; voltage ranges from 1.08V and 1.32V (1.2V nominal). The associated ground pin for this supply is the GNDOSC32 pin. Required for all operational modes. * AVDD pin: Powers the 10-bit Analog to Digital Converter and associated cells; voltage ranges from 3.0V and 3.6V (3.3V nominal). The associated ground pin for this supply is the AGND pin.
5.2
Power Consumption
Note: The following figures are preliminary figures based on prototype silicon. They are subject to change for the production silicon.
The AT91CAP7 consumes about 600 A of static current on VDDCORE at typical conditions (1.2V, 25C). On VDDBU, the current does not exceed 30 A at typical conditions. For dynamic power consumption, the AT91CAP7 consumes about 0.33 mW/MHz of power or 275 A/MHz of current on VDDCORE at typical conditions (1.2V, 25C) and with the ARM subsystem running full-performance algorithm with on-chip memories, and no peripherals active.
5.3
Power Supply Isolation
All power supplies must be active in normal operation. CAP7 supports a low power backup mode in which most of the core including the processor can be powered down. In backup mode, it is mandatory to keep VDDBU and VDDOSC32 active; all other supplies must be inactive.
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6. I/O Line Considerations
6.1 JTAG Port Pins
TMS and TDI are Schmitt trigger inputs with pull-up resistors. TCK is a Schmitt trigger input with pull-down resistor. TDO is an output, driven at up to VDDIO, with a pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 100kohm to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in the Reset Pins paragraph. JTAGSEL is supplied with VDDBU, all other JTAG signals are supplied with VDDIO.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 100 k to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIO. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor for both ARM core and boundary scan. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 k minimum to VDDIO.
6.4
PIO Controllers
All the I/O lines which are managed by a PIO Controller integrate a programmable pull-up resistor of 100 k minimum. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that must be enabled as Peripheral at reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing tables.
6.5
Shut Down Logic pins
The SHDW pin is an output only, which is driven by the Shut Down Controller only at low level. It can be tied high with an external pull-up resistor at VDDBU only.
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7. Processor and Architecture
7.1 ARM7TDMI Processor
* RISC Processor Based on ARMv4T Von Neumann Architecture
- Runs at up to 80 MHz, providing up to 72 MIPS * Two instruction sets - ARM high-performance 32-bit Instruction Set - Thumb high code density 16-bit Instruction Set * Three-stage pipeline architecture - Instruction Fetch (F) - Instruction Decode (D) - Execute (E)
7.2
Debug and Test Features
* Integrated embedded in-circuit emulator
- Two watchpoint units - Test access port accessible through a JTAG protocol - Debug communication channel * Debug Unit - Two-pin UART - Debug communication channel interrupt handling - Chip ID and EXTended Chip ID Register * IEEE1149.1 JTAG Boundary-scan on all digital pins, except reset, backup reset, and test pins
7.3
Bus Matrix
* 6 Layers Matrix, handling requests from 6 masters * Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master * Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support * One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap * Boot Mode Select - Non-volatile Boot Memory can be internal or external - Selection is made by BMS pin sampled at reset * Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory - Allows Handling of Dynamic Exception Vectors
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7.3.1 Matrix Masters The Bus Matrix of the AT91CAP7 manages six Masters, which means that each master can perform an access concurrently with others, as long as the slave it accesses is available. Each Master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decoding. There are four independent masters available for the Metal Programmable Block (MP Block). Table 7-1.
Master 0 Master 1 Master 2 Master 3 Master 4 Master 5
List of Bus Matrix Masters
ARM7TDMI Peripheral DMA Controller MP Block Master A MP Block Master B MP Block Master C MP Block Master D
7.3.2
Matrix Slaves The Bus Matrix of the AT91CAP7 manages ten Slaves. Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave. There are four independent slaves available for the Metal Programmable Block (MP Block). Table 7-2.
Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 Slave 8 Slave 9
List of Bus Matrix Slaves
Internal SRAM 96 Kbytes Internal SRAM 64 Kbytes Internal ROM 256 Kbytes MP Block Slave A MP Block Slave B MP Block Slave C MP Block Slave D MP Block Slave for ARM control of AHB masters* External Bus Interface Peripheral Bridge
* Note: Slave7 may only be accessed by the ARM7TDMI master and can be used to access control and status registers for AHB master devices in the metal programmable block that do not also have APB connections for this purpose.
7.4
Peripheral DMA Controller
* Acting as one Matrix Master * Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. * Next Pointer Support, avoids strong real-time constraints on buffer management. * 22 channels - Two for each USART
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- Two for the Debug Unit - Two for the Serial Peripheral Interface - One for the Analog to Digital Converter (ADC) - 13 for peripherals implemented in the Metal Programmable Block
8. Memories
8.1 Embedded Memories
* 256 Kbyte Fast ROM - Single Cycle Access at full matrix speed * 96 Kbyte Fast SRAM - Single Cycle Access at full matrix speed * 64 Kbyte Fast SRAM - Single Cycle Access at full matrix speed * Two 4 Kbyte DPRAMs - Accessed from the Metal Programmable Block
8.2
Memory Mapping
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 9 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS7. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access.
Figure 8-1.
AT91CAP7 Product Memory Mapping
256M Bytes 8 x 256M Bytes 2,048M bytes
0x0000 0000
0x0FFF FFFF
Internal Memories External Bus Interface Chip Select 0 to 7 Undefined (Abort)
0x1000 0000
0x8FFF FFFF
0x9000 0000 6 x 256M Bytes 1,536M Bytes
0xEFFF FFFF
256M Bytes
0xF000 0000
0xFFFF FFFF
Internal Peripherals
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Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 (ARM7TDMI), two different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot and one for external boot.
8.3
8.3.1
Internal Memory Mapping
Internal 160-kBytes Fast SRAM The AT91CAP7 embeds 160-Kbytes of high-speed SRAM configured in blocks of 96 KB and 64KB. When accessed from the AHB, each SRAM block is independently single cycle accessible at full matrix speed (MCK). Boot Memory The remappable memory area is between 0x0 and 0x000F FFFF. If BMS is detected at logic 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. The default configuration for the Static Memory Controller, byte select mode, 16-Bit data bus, Read/Write controlled by Chip Select, allows the device to boot on 16Bit nonvolatile memory. If BMS is detected at logic 1, the boot memory is the embedded ROM.
8.3.2
8.4
Boot Program
The internal 256 KB ROM is metal-programmable and each AT91CAP7 customer may develop their own boot program using their own code or a combination of their own code and routines available from Atmel.
8.5
External Memories Mapping
The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-MByte memory area assigned.
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Figure 8-2.
AT91CAP7 External Memory Mapping
256M Bytes 256M Bytes 256M Bytes 0x1000 0000
0x1FFF FFFF
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
EBI_NCS0 EBI_NCS1 or EBI_SDCS EBI_NCS2 EBI_NCS3 EBI_NCS4 EBI_NCS5 EBI_NCS6 EBI_NCS7 SmartMedia or NAND Flash EBI CompactFlash EBI Slot 0 CompactFlash EBI Slot 1
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
8.6
External Bus Interface
* Optimized for Application Memory Space support * Integrates two External Memory Controllers: - Static Memory Controller - SDRAM Controller * Additional logic for NANDFlash and CompactFlashTM * Optional Full 32-bit External Data Bus * Up to 26-bit Address Bus (up to 64MBytes linear per chip select) * Up to 6 chips selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support
8.6.1
Static Memory Controller * 8-, 16- or 32-bit Data Bus * Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) * Multiple device adaptability - Compliant with LCD Module - Control signals programmable setup, pulse and hold time for each Memory Bank * Multiple Wait State Management - Programmable Wait State Generation - External Wait Request
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- Programmable Data Float Time * Slow Clock mode supported 8.6.2 SDRAM Controller * Supported devices: - Standard SDRAM * Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Data Path * Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multi-bank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable * Energy-saving capabilities - Self-refresh, power down and deep power down modes supported * Error detection - Refresh Error Interrupt * SDRAM Power-up Initialization by software * CAS Latency of 1, 2 and 3 supported * Auto Precharge Command not used
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9. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also includes control registers for configuring the AHB Matrix and the chip configuration. The chip configuration registers allow setting the EBI chip select assignment for external memories.
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9.1 System Controller Block Diagram
AT91CAP7 System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq1 fiq periph_irq[2..29] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset UDPCK VDDBU POR VDDBU Powered SLCK Real-Time Timer RC OSC SLCK SHDN WKUP0 backup_nreset XIN32 XOUT32 SLOW CLOCK OSC rtt_alarm 20 General-Purpose Backup Registers Shut-Down Controller periph_clk[11..29] periph_nreset periph_irq[11..29] MAINCK SLCK SLCK int XIN XOUT PLLRCA MAIN OSC PLLA PLLB MAINCK Power Management Controller periph_clk[2..29] pck[0-3] PCK UDPCK UHPCK PLLACK PLLBCK MCK PCK User Metal Programmable Block rtt_irq rtt_alarm periph_clk[24] periph_nreset periph_irq[24] USB Device Port Debug Unit dbgu_irq dbgu_txd Advanced Interrupt Controller int por_ntrst ntrst ARM7TDMI nirq nfiq
Figure 9-1.
proc_nreset PCK debug
pit_irq jtag_nreset wdt_irq MCK periph_nreset Bus Matrix Boundary Scan TAP Controller
SLCK backup_nreset
PLLACK PLLBCK
UHPCK MCK pmc_irq
periph_nreset idle
periph_clk[4..10] periph_nreset
periph_nreset periph_clk[2..3] dbgu_rxd PA0-PA31
PIO Controllers
periph_irq[2..3] irq0-irq1 fiq dbgu_txd
periph_irq[4..10]
Embedded Peripherals
in out enable
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9.2
System Controller Mapping
The System Controller's peripherals are all mapped within the highest 16K bytes of address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. This allows addressing all the registers of the System Controller from a single pointer by using the standard ARM instruction set since the Load/Store instructions have an indexing mode of +/4kbytes. Figure 9-2 shows where the User Interfaces for the System Controller peripherals fit into the memory map (relative to bus matrix and EBI (SMC, SDRAMC).
Figure 9-2.
System Controller Mapping
0xFFFF C000 Reserved 0xFFFF E9FF 0xFFFF EA00 SDRAMC 0xFFFF EBFF 0xFFFF EC00 SMC 0xFFFF EDFF 0xFFFF EE00 MATRIX 0xFFFF EFFF 0xFFFF F000 AIC 0xFFFF F1FF 0xFFFF F200 DBGU 0xFFFF F3FF 0xFFFF F400 PIOA 0xFFFF F5FF 0xFFFF F600 PIOB 0xFFFF F7FF 0xFFFF F800 Reserved 0xFFFF FBFF 0xFFFF FC00 PMC 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 GPBR 0xFFFF FDB0 Reserved 0xFFFF FFFF Reserved RSTC SHDC RTT PIT WDT OSCMR Power Management Controller Reset Controller Shut-Down Controller Real-Time Timer Periodic Interval Timer Watchdog Timer Oscillator Mode Register General-Purpose Backup Registers 512 bytes/128 words 16 bytes/4 words 16 bytes/4 words 16 bytes/4 words 16 bytes/4 words 16 bytes/4 words 2 bytes/1 words (3words reserved) 80 bytes/20 words Reserved Parallel I/O Controller B 512 bytes/128 words Parallel I/O Controller A 512 bytes/128 words Debug Unit 512 bytes/128 words Advanced Interrupt Controller 512 bytes/128 words Matrix 512 bytes/128 words Static Memory Controller 512 bytes/128 words SDRAM Controller 512 bytes/128 words Peripheral Name Size
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9.3 Reset Controller
* Based on two Power-on-Reset cells - one on VDDBU and one on VDDCORE * Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset * Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices
9.4
Shut Down Controller
* Shut-Down and Wake-Up logic - Software programmable assertion of the SHDW open-drain pin - De-assertion Programmable on a WKUP0 pin level change or on alarm
9.5
Clock Generator
* Embeds the Low Power, fast start-up 32kHz RC Oscillator - Provides the default Slow Clock SLCK to the system - The SLCK is required for AT91CAP7 to start-up because it is the default clock for the ARM7TDMI at power-up. * Embeds the Low Power 32768Hz Slow Clock Oscillator - Requires an external 32768Hz crystal - Optional Slow Clock SLCK source when a real-time timebase is required * Embeds the Main Oscillator - Requires an external crystal. For systems using the USB features, 12MHz is recommended. - Oscillator bypass feature - Supports 8 to 16MHz crystals. 12 MHz crystal is required if using the USB features of AT91CAP7. - Generates input reference clock for the two PLLs. * Embeds PLLA primarily for generating processor and master clocks. For full-speed operation on the ARM7TDMI processor, this PLL should be programmed to generate a 160 MHz clock that must then be divided in half to generate the 80 MHz PCK and related clocks. - PLLA outputs an 80 to 240MHz clock - Requires an external RC filter network - PLLA has a 1MHz minimum input frequency - Integrates an input divider to increase output accuracy * Embeds PLLB primarily for generating a 96 MHz clock that is divided down to generate the USB related clocks. - PLLB and its internal low-pass filter (LPF) are tuned especially for generating a 96 MHz clock with a 12 MHz input frequency - 12 MHz minimum input frequency - Integrates an input divider to increase output accuracy
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Figure 9-3.
Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XIN XOUT Slow Clock Oscillators
RC & XTAL
Slow Clock SLCK
Main Oscillator
Main Clock MAINCK
PLLRCA
PLL and Divider A PLL and Divider B LPF
PLLA Clock PLLACK PLLB Clock PLLBCK
Status
Control
Power Management Controller
9.6
Power Management Controller
* The Power Management Controller provides the following clocks as shown in Figure 7 below: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces - the USB Device Clock UDPCK - independent peripheral clocks (periph_clk), typically at the frequency of MCK - four programmable clock outputs: PCK0 to PCK3 * Five flexible operating modes: - Normal Mode, processor and peripherals running at a programmable frequency - Idle Mode, processor stopped waiting for an interrupt - Slow Clock Mode, processor and peripherals running at low frequency - Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt - Backup Mode, Main Power Supplies off, VDDBU and VDDOSC32 on
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Figure 9-4. AT91CAP7 Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int
periph_clk[..]
Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..]
USB Clock Controller ON/OFF PLLBCK Divider /1,/2,/4 ON/OFF UDPCK UHPCK
9.7
Periodic Interval Timer
* Includes a 20-bit Periodic Counter * Includes a 12-bit Interval Overlay Counter * Real Time OS or Linux/WinCE compliant tick generator
9.8
Watchdog Timer
* 16-bit key-protected only-once-Programmable Counter * Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.9
Real-Time Timer
* One Real-Time Timer, allowing backup of time - 32-bit Free-running, back-up Counter - Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz oscillator - Alarm Register capable to generate a wake-up of the system through the Shut Down Controller
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9.10
General-Purpose Backed-up Registers
* Twenty 32-bit backup general-purpose registers
9.11
Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor * Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive * Two External Sources plus the Fast Interrupt signal * 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector * Protect Mode - Easy debugging by preventing automatic operations when protect models are enabled * Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
9.12
Debug Unit
* Composed of two functions - Two-pin UART - Debug Communication Channel (DCC) support * Two-pin UART - Implemented features are 100% compatible with the standard Atmel USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter * Debug Communication Channel Support - Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor's ICE Interface
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9.13 Chip Identification
* Chip ID: 837709xx (0x1000 0011 0111 0111 0000 1001 010x xxxx). This value is stored in the Chip ID Register (DBGU_CIDR) in the Debug Unit. The last 5 bits of the register are reserved for a chip version number. This module contains two 32 bit wide hardware registers which are mapped into three fields: cap7_version - CAP7 platform hardware version ( DBGU_EXID[31:30], DBGU_CIDR[4:0] ) cap7_id - Defines device to debugger software ( DBGU_CIDR[31:5] ) mp_chip_id - user defined value for MP customization ( DBGU_EXID[29:0]) * Ext Chip ID: Bits 29:0 are MPBlock programmable. Bits 31:30 are resevered. * JTAG ID: unique for each CAP7 personalization.
9.14
PIO Controllers
* One PIO Controller (PIOA) included. * Optionally, as many as 3 additional PIO controllers may be added to the MPBlock. * Each PIO Controller controls up to 32 programmable I/O Lines - PIOA controls 32 I/O Lines (PA0 - PA31) - PIOB can control up to 32 of the MPIO Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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9.15
9.15.1
User Interface
Special System Controller Register Mapping Special System Controller Registers
Register Oscillator Mode Register General Purpose Backup Register 1 --General Purpose Backup Register 20 Name SYSC_OSCMR SYSC_GPBR1 --SYSC_GPBR20 Access Read/Write Read/Write --Read/Write Reset Value 0x1 0x0 --0x0
Table 9-1.
Offset 0x50 0x60 --0xAC
9.15.2 Oscillator Mode Register Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
SYSC_OSCMR Read/Write
0x00000001
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 OSC32K_SEL 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 OSC32K_XT _ EN 24 - 16 - 8 - 0 OSC32K_RC _ EN
* OSC32K_RC_EN: Enable internal RC oscillator 0: No effect. 1: Enables the internal RC oscillator [enabled out of reset indicating system starts off of RC] * OSC32K_XT_EN: Enable external crystal oscillator 0: No effect. 1: Enables the external crystal oscillator * OSC32K_SEL: Slow clock source select 0: Selects internal RC as source of slow clock 1: Selects external crystal and source of slow NOTE: After setting the OSC32K_XT_EN bit, wait the 32 kHz Crystal Oscillator Startup Time (see table 34-5) on slow clock timing before setting the OSC32K_SEL bit.
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9.15.3 General Purpose Backup Register Register Name: SYSC_GPBRx Access Type: Reset Value:
31
Read/Write 0x0
30 29 28 GPBRx 27 26 25 24
23
22
21
20 GPBRx
19
18
17
16
15
14
13
12 GPBRx
11
10
9
8
7
6
5
4 GPBRx
3
2
1
0
* GPBRx: General Purpose Backup Register These are user programmable registers that are powered by the backup power supply (VDDBU).
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10. Peripherals
10.1 Peripheral Mapping
Both the standard peripherals and any APB peripherals implemented in the MPBlock are mapped in the upper 256M bytes of the address space between the addresses 0xFFFA 0000 and 0xFFFE FFFF. Each User Peripheral is allocated 16K bytes of address space as shown below in Figure 10-1.
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Figure 10-1. AT91CAP7 Peripheral Mapping
Peripheral Name 0xFFFA 0000
0xFFFA 3FFF
Size 16K Bytes
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
0xFFFA 4000 UDP
0xFFFA 7FFF
USB Device Port
16K Bytes
0xFFFA 8000 ADC
0xFFFA BFFF
Analog to Digital Converter
16K Bytes
0xFFFA C000
0xFFFA FFFF
SPI0
Serial Peripheral Interface 0
16K Bytes
0xFFFB 0000 USART0
0xFFFB 3FFF
Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 MP Block Peripheral 0
16K Bytes
0xFFFB 4000 USART1
0xFFFB 7FFF
16K Bytes 16K Bytes
0xFFFB 8000 MPP0
0xFFFB BFFF
0xFFFB C000
0xFFFB FFFF
MPP1
MP Block Peripheral 1
16K Bytes
0xFFFC 0000
0xFFFC 3FFF
MPP2
MP Block Peripheral 2
16K Bytes
0xFFFC 4000
0xFFFC 7FFF
MPP3
MP Block Peripheral 3
16K Bytes
0xFFFC 8000
MPP4
MP Block Peripheral 4
16K Bytes
0xFFFC BFFF
0xFFFC C000
0xFFFC FFFF
MPP5
MP Block Peripheral 5
16K Bytes
0xFFFD 0000
MPP6
MP Block Peripheral 6
16K Bytes
0xFFFD 3FFF
0xFFFD 4000
0xFFFD 7FFF
MPP7
MP Block Peripheral 7
16K Bytes
0xFFFD 8000
MPP8
MP Block Peripheral 8
16K Bytes
0xFFFD BFFF
0xFFFD C000
MPP9
MP Block Peripheral 9
16K Bytes
0xFFFD FFFF
0xFFFE 0000
MPP10
MP Block Peripheral 10
16K Bytes
0xFFFE 3FFF
0xFFFE 4000
MPP11
MP Block Peripheral 11
16K Bytes
0xFFFE 7FFF
0xFFFE 8000
MPP12
MP Block Peripheral 12
16K Bytes
0xFFFE BFFF
0xFFFE C000
MPP13
MP Block Peripheral 13
16K Bytes
0xFFFE FFFF
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10.2
Peripheral Identifiers
The AT91CAP7 embeds some of the most common peripherals. Additional peripherals can be implemented in the Metal Programmable Block as required by the customer. The table below defines the Peripheral Identifiers of the AT91CAP7. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 10-1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
AT91CAP7 Peripheral Identifiers
Peripheral Mnemonic AIC SYSC PIOA PIOB US0 US1 SPI0 TC0 TC1 TC2 UDP ADC MPP0 MPP1 MPP2 MPP3 MPP4 MPP5 MPP6 MPP7 MPP8 MPP9 MPP10 MPP11 MPP12 MPP13 MPMA MPMB MPMC Peripheral Name Advanced Interrupt Controller System Controller Parallel I/O Controller A Optional Parallel I/O Controller B USART 0 USART 1 Serial Peripheral Interface 0 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 USB Device Port Analog to Digital Converter Metal Programmable Block Peripheral 0 Metal Programmable Block Peripheral 1 Metal Programmable Block Peripheral 2 Metal Programmable Block Peripheral 3 Metal Programmable Block Peripheral 4 Metal Programmable Block Peripheral 5 Metal Programmable Block Peripheral 6 Metal Programmable Block Peripheral 7 Metal Programmable Block Peripheral 8 Metal Programmable Block Peripheral 9 Metal Programmable Block Peripheral 10 Metal Programmable Block Peripheral 11 Metal Programmable Block Peripheral 12 Metal Programmable Block Peripheral 13 Metal Programmable Block Master A Metal Programmable Block Master B Metal Programmable Block Master C External Interrupt FIQ
Peripheral ID
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AT91CAP7S450A [Preliminary]
Table 10-1.
29 30 31
AT91CAP7 Peripheral Identifiers (Continued)
Peripheral Mnemonic MPMD AIC AIC Peripheral Name Metal Programmable Block Master D Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt
Peripheral ID
10.3
10.3.1
Peripheral Interrupts and Clock Control
System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: * the SDRAM Controller * the Debug Unit * the Periodic Interval Timer * the Real-Time Timer * the Watchdog Timer * the Reset Controller * the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller.
10.3.2
External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. Timer Counter Interrupts The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 7 of the Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine. The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 7 disables the clock of the 3 channels.
10.3.3
10.4
Peripherals Signals Multiplexing on I/O Lines
The AT91CAP7 features up to two PIO controllers, PIOA which multiplexes the I/O lines of the standard peripheral set and the optional PIOB which can multiplex I/O for any peripherals or user logic included in the MPBlock. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on PIOA. The column "Reset State" indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is listed, the PIO Line resets in input mode with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets high. 39
5119DS-CAP-05/09
If a signal name is listed in the "Reset State" column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 10.4.1 PIO Controller A Multiplexing Table 10-2.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28
Multiplexing on PIO Controller A
Peripheral A FIQ NWAIT NCS4/CFCS0 CFCE1 A25/CFRNW NANDOE NANDWE NCS6 NCS7 ADTRG IRQ0 IRQ1 NCS5/CFCS1 CFCE2 A23 A24 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 Peripheral B DBG_DRXD DBG_DTXD USART0_SCK0 USART0_RTS0 USART0_CTS0 USART0_TXD0 USART0_RXD0 SPI_MISO SPI_MOSI SPI_SPCK SPI_NPCS0 SPI_NPCS1 SPI_NPCS2 SPI_NPCS3 APMC_PCK0 APMC_PCK1 APMC_PCK2 APMC_PCK3 USART1_SCK1 USART1_RTS1 USART1_CTS1 USART1_TXD1 USART1_RXD1 TIMER0_TCLK0 TIMER1_TCLK1 TIMER2_TCLK2 TIMER0_TIOA0 TIMER0_TIOB0 TIMER1_TIOA1 Reset State I/O I/O I/O I/O Periph driven low with pullup enabled I/O I/O I/O I/O I/O I/O I/O I/O I/O Periph A, driven low with pullup enabled Periph A, driven low with pullup enabled I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PIO Controller A
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AT91CAP7S450A [Preliminary]
Table 10-2.
I/O Line PA29 PA30 PA31
Multiplexing on PIO Controller A
Peripheral A D29 D30 D31 Peripheral B TIMER1_TIOB1 TIMER2_TIOA2 TIMER2_TIOB2 Reset State
PIO Controller A
10.4.2
PIO Controller B Multiplexing If implemented, the PIOB Port is dedicated fully to the MPBlock, and its multiplexing is determined by the MPBlock "personality." Resource Multiplexing EBI If not required, the NWAIT function (external wait request) can be deactivated by software allowing this pin to be used as a PIO. Use of the NWAIT function prevents use of the Debug Unit.
10.4.3 10.4.3.1
10.4.3.2
32-bit Data Bus Using a 32-bit Data Bus prevents: * using the three Timer Counter channels' outputs and trigger inputs * using the USART1 * using two of the clock outputs (APMC_PCK2 and APMC_PCK3)
10.4.3.3
NAND Flash Interface Using the NAND Flash interface prevents using the NCS3 and USART0. Compact Flash Interface Using the CompactFlash interface prevents using the USART0. SPI Using the SPI prevents use of NCS6, NCS7, and the ADC external trigger.
10.4.3.4
10.4.3.5
10.4.3.6
USARTs Using the USART0 prevents use of CompactFlash or NAND Flash. Using the USART1 prevents using a full 32-bit bus for the EBI.
10.4.3.7
Clock Outputs Using the clock outputs prevents use of either higher EBI address bits or a full 32-bit data bus (see table 10-2). Interrupt Lines Using FIQ prevents using the Debug Unit. Using IRQ0 prevents the use of SPI_NPCS0. Using IRQ1 prevents the use of SPI_NPCS1.
10.4.3.8
41
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10.5
10.5.1
Embedded Peripherals Overview
Serial Peripheral Interface * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
10.5.2
USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB-first or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter time-guard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo
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AT91CAP7S450A [Preliminary]
10.5.3 Timer Counter * Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels 10.5.4 USB Device Port * USB V2.0 full-speed compliant, 12 MBits per second * Embedded USB V2.0 full-speed transceiver * Embedded 2,432-byte dual-port RAM for endpoints * Suspend/Resume logic * Ping-pong mode (two memory banks) for isochronous and bulk endpoints * Six general-purpose endpoints - Endpoint 0 and 3: 64 bytes, no ping-pong mode - Endpoint 1 and 2: 64 bytes, ping-pong mode - Endpoint 4 and 5: 512 bytes, ping-pong mode 10.5.5 Analog to Digital Converter * 10-bit Successive Approximation Register (SAR) ADC based on thermometric-resistive * Up to 440 kSamples/sec. * Up to 8 independent analog input channels * Low active power: < 2 mW * Low power stand-by mode * External voltage reference of 2.6V to analog supply for better accuracy * + 2LSB Integral Non-Linearity (INL), + 0.9 LSB Differential Non-Linearity (DNL) * Individual enable and disable of each channel * Multiple trigger sources: - Hardware or software trigger - External trigger pin * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 43
5119DS-CAP-05/09
11. Metal-Programmable Block
The Metal Programmable Block (MPBlock) is connected to internal resources such as the AHB bus or Advanced Interrupt Controller and external resources such as dedicated I/O pads or a PIO controller. The MPBlock may be used to implement Advanced High-speed Bus (AHB) or Advanced Peripheral Bus (APB) custom peripherals. The MPBlock provides approximately 450K gates of standard cell custom logic for the addition of user IP to the AT91CAP7 implementation. Each custom metal mask set for the MPBlock can be referred to as a "personality."
11.1
Internal Connectivity
In order to connect the MPBlock custom peripherals to the AT91CAP7 platform design, various connections to the MPBlock are provided as shown in the figure and described below.
Figure 11-1. MP Block Interface Diagram
MP Block
4x4 AHB Slaves
4 AHB Masters
15 APB Slaves
MP Interface - Scan Wrapper
... ...
ChipID Ext ChipID
USB PHY
Clocks (42) Interrupts (19)
MPBlock Custom AREA
BIST BIST
DPR 2kx16
PDC Channels (13)
DPR 2kx16
Resets (4)
Chip Boundary Scan
MPIOs (90)
11.1.1
AHB Master Buses The CAP7 MPBlock may implement up to four independent AHB masters each having a dedicated AHB master bus connected to the AHB Matrix.
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AT91CAP7S450A [Preliminary]
11.1.2 AHB Slave Buses The CAP7 MPBlock receives four independent AHB slave buses coming from the AHB Matrix. Each bus has four select signals allowing up to 16 AHB slaves to be implemented in the MPBlock. Clocks The MPBlock receives a total of 42 clocks including the following: 32768 Hz Slow Clock 8-16 MHz Main Oscillator Clock PLLA Clock PLLB Clock 12 and 48 MHz USB Host Clock (UHPCK) for optional full-speed USB Host Port in MPBlock MCK System Clock PCK System Clock 14 gated APB peripheral clocks for use by Peripherals with ID 12 to 25, including 1 dedicated Peripheral and Configuration clock for an additional PIO controller. 4 gated clocks (for AHB masters) associated with ID 26 to 29. 11.1.4 Interrupts The MPBlock is connected to 19 interrupt lines corresponding to Peripheral ID 11 to 29. 11.1.5 Peripheral DMA Channels The MPBlock is connected to 13 channels of the Peripheral DMA Controller; 5 read channels, 5 write channels, 3 read/write channel.
11.1.3
11.2
11.2.1
External Connectivity
The MPBlock is connected to the following external resources. PIO Controller B The MPBlock may instantiate one 32-bit wide PIO Controller (PIOB) and connect any available signals to the alternate functions A and B of PIOB allowing the addition of up to 32 simultaneous custom I/O and up to 64 custom I/O connections. Dedicated I/O The MPBlock is directly connected to up to 90 dedicated I/O Pads with the following features: Pull-up, Pull-down, bus holder Control Pins The number of dedicated I/O's for the MPBlock is determined by the package selection.
11.2.2
11.3
Prototyping Solution
Customer's CAP7-based designs can be prototyped using the Atmel AT91CAP7X-DK (Development Kit) using a AT91CAP7S emulation-enabled CAP7 device and a Xilinx Virtex-IV XC4LX80FFG1148 FPGA. User logic can be added to this large FPGA and debugged using standard software development tools and JTAG-enabled, In-Circuit Emulation (ICE devices).
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5119DS-CAP-05/09
12. AT91CAP7 Ordering Information
Table 12-1. AT91CAP7 Ordering Information
Package BGA225 Package Type RoHS Compliant Temperature Operating Range Industrial -40C to 85C
Ordering Code AT91CAP7S450A-CJ
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5119DS-CAP-05/09
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5119DS-CAP-05/09

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